The present invention generally relates to a semiconductor device fabricating method, and more particularly, to a method of fabricating a field-effect transistor employing a substrate having an SOI (Silicon-on-Insulator) layer, or a silicon layer formed on a supporting substrate with an insulating film interposed therebetween (the substrate including a SOI layer will be referred to as a "SOI substrate" hereinafter), especially a field-effect transistor employing an SOI substrate whose SOI layer has a recessed structure.
LSIs in which field-effect transistors using a bulk silicon substrate as a base are integrated have been developed to have a faster operating speed and/or a lower consumption power with a fine structure. The fineness of the LSIs has been promoted on the basis of a scaling law. However, when the element size is reduced to a level of 0.1 .mu.m or lower, an increased substrate impurity concentration of 10.sup.18 cm.sup.-3 or more is required for good element isolation.
When the substrate impurity concentration is increased to a value as described above, carrier mobility is reduced significantly. Therefore, an increase in current drive capacity can be hardly expected. This consequently causes a problem that a high performance, which is an advantage provided by the promotion of fineness, cannot be attained. In view of the above, there has been proposed a field-effect transistor formed on an SOI substrate. When forming the transistor on the SOI substrate, the element isolation is achieved not by junction but by a buried oxide film. Therefore, the substrate impurity concentration is suppressed low, so that the carrier mobility can be prevented from being significantly reduced. There is also produced an effect that the junction capacitance is reduced.
The above arrangement consequently enables the achievement of a high performance with promoted fineness. If the SOI layer is sufficiently reduced in thickness by forming a recess in the SOI layer in a portion which becomes a channel, the field-effect transistor formed on the SOI substrate has an improved mobility of carriers because of the fully depletion of the SOI layer. Furthermore, by virtue of the SOI layer formed to a reduced thickness, the field-effect transistor provides an advantage that the short channel effect is remarkably suppressed.
However, in order to achieve a high performance with the SOI structure, it is required that a problem of reducing the parasitic resistance is solved, and without solving this problem, there is no possibility of achieving a high drive current capacity in the SOI transistors.
Furthermore, for the achievement of fineness and a low resistance, it is necessary to use a salicide (self-aligned-silicide) process as a method of making a source region and a drain region have a low resistance. The salicide process is a process which utilizes a phenomenon that metal easily reacts with silicon and hardly reacts with a silicon oxide. The salicide process includes the steps of, after forming a LOCOS (LOCal Oxidation of Silicon) oxide film, a gate electrode and an oxide (or nitride) on side surfaces of the gate electrode by an ordinary process, forming a high-melting-point metal film on the whole surface of the wafer, subjecting it to a heat treatment to thereby form a silicide only in silicon-exposed portions, and removing an unreacted metal film selectively to thereby provide a low-resistance silicide only on the surfaces of the source region and the drain region (and/or a polycrystalline silicon gate electrode). There exists no technique which considers the thickness of the source and drain regions with the intention of obtaining a stable silicide in applying the salicide technique to an SOI transistor having a fully depletion operation.
However, in the case where the whole SOI layer is made to have a thickness required for the fully depletion without using the recessed structure, i.e., in the case of an SOI layer of which the thickness in the source and drain regions is as thin as that of the channel portion, it is difficult to obtain a uniform, stable crystalline phase C54 of a silicide of a high-melting-point metal such as titanium, because of the occurrence of a high resistance due to agglomeration.
When the high-melting-point metal film is thin, a phase shift from a quasi-stable high-resistance phase C49 of the high-melting-point metal silicide to the low-resistance phase C54 is insufficient. In this case, a temperature nonuniformity in the substrate surface in an annealing process and/or a thickness nonuniformity due to sputtering of a high-melting-point metal such as Ti prior to the annealing process easily affect the resistance in the substrate surface, consequently making it a nonuniform one.
Furthermore, when the silicide is thin, a contact may disadvantageously penetrate the silicide in the contact processing stage, causing a high contact resistance.
For these reasons, when the salicide technique is adopted, it is difficult to fabricate a field-effect transistor on an SOI substrate without using the recessed structure.
Next, methods of fabricating a field-effect transistor formed on an SOI layer of the recessed structure utilizing techniques disclosed in Japanese Patent Laid-Open Publication No. HEI 8-83913 will be described with reference to FIGS. 5A, 5B, 5C and 5D and FIGS. 6A, 6B, 6C and 6D. Note that the structure described in the above document is a structure in which the SOI layer in source and drain regions is made sufficiently thick to reduce the parasitic resistance and the SOI layer in a channel portion is made sufficiently thin to achieve a fully depletion.
First of all, a first fabricating method will be described with reference to FIGS. 5A through 5D.
In the first fabricating method, first, a silicon oxide film 35 is formed on an SOI substrate which is comprised of a silicon substrate 31, a buried silicon oxide film 32 and an SOI layer 33. Next, by means of an LPCVD (Low Pressure Chemical Vapor Deposition) method, a silicon nitride film 34 is deposited on the silicon oxide film 35. Then, resist is patterned to be opened at a portion corresponding to the channel region, and the silicon nitride film 34 there is removed, thus providing a structure as shown in FIG. 5A.
Next, by performing oxidation, the SOI layer 33 in a position corresponding to the channel region only is made thin. This oxidation can be controlled with an accuracy of 10 .ANG.. Therefore, the oxidation condition can be properly optimized so that the thickness of a finally obtained channel region has a desired value. Thus, a structure as shown in FIG. 5B is obtained. Reference numeral 35a denotes a LOCOS oxide film. Then, the silicon nitride film 34, the silicon oxide film 35 and the LOCOS oxide film 35a are removed, thereby obtaining a structure having a cross-sectional view as shown in FIG. 5C.
Finally, gate oxidation is performed according to a common field-effect transistor fabricating process, thereby forming a gate oxide film 37. Next, processing of a gate electrode 36 and ion implantation into the source and drain regions are performed, thereby achieving a structure as shown in FIG. 5D.
A second fabricating method will be described next with reference to FIGS. 6A through 6D.
First, an element isolation LOCOS oxide film 41 is formed on an SOI substrate consisting of a silicon substrate 44, a buried silicon oxide film 43 and an SOI layer 42 according to a common field-effect transistor forming process, thereby obtaining an element isolation structure having a cross section as shown in FIG. 6A. Next, a resist formed on the SOI layer 42 is patterned to be opened at a portion which corresponds to a channel region so that the SOI layer 42 is partially etched away. At this time, the etching conditions are optimized such that the thickness of the channel region finally has a desired value. In this way, the channel region is formed between a source region and a drain region.
Next, the patterning resist is removed, thereby obtaining a structure having a cross-section as shown in FIG. 6B. Subsequently, a surface of the SOI layer 42 constituting the channel region, source region and drain region are oxidized to form a silicon oxide film 45, and then a silicon nitride film 46 is deposited on it. Further, the silicon nitride film 46 is selectively removed by anisotropic etching, so that the silicon nitride film 46 is left only on the side surfaces of raised portions at the boundary between the channel region and the source region and at the boundary between the channel region and the drain region, respectively. Through the above steps, a structure having a cross-section as shown in FIG. 6C is obtained. Finally, a gate electrode material is deposited on the whole wafer surface to form a buried gate electrode 47 by a etch-back process. Finally, ion implantation into the source region and the drain region is performed. Thus, a structure as shown in FIG. 6D is completed.
A further technique has also been proposed, which is shown in FIGS. 7A, 7B, 7C and 7D.
First, as shown in FIGS. 7A and 7B, a channel portion is subjected to the LOCOS process so that an SOI film 52 is recessed. It is to be noted that the cross-sectional structure shown in FIG. 7A is identical to that of FIG. 5A, and in FIG. 7A, reference numeral 51 denotes a silicon nitride film, reference numeral 53 denotes a buried silicon oxide film, reference numeral 54 denotes a silicon Hsubstrate, and reference numeral 55 denotes a silicon oxide film. Subsequently, as shown in FIG. 7C, a gate oxide film 58 is formed without removing the silicon nitride film 51 which serves as a film for restraining or pressing the LOCOS oxide film, and then a CVD polycrystalline silicon film 56 is formed on the whole wafer surface. Subsequently, the polycrystalline silicon film 56 is etched back to the surface of the silicon nitride film 51. Then a source region and a drain region are formed according to a common process. In this way, an SOI transistor having a recessed structure is completed as shown in FIG. 7D, where reference numeral 57 denotes a silicon oxide film.
In the meanwhile, in order to cope with the fineness of LSIs which will be promoted more and more, the following requirements or conditions should be met. It is to be noted that the term "LOCOS ends" appearing below denotes SOI layer portions defined by LOCOS oxide end portions including no flat LOCOS bottom, the LOCOS oxide end portions including the whole bird's beak.
In the first place, in forming a transistor having a recessed structure by a currently available technique, to reduce damage of the SOI layer surface at the channel forming portion, it is necessary to use not the dry etching process but the LOCOS technique.
In the second place, when the LOCOS technique is used, it is required that the gate electrode is formed inside of the LOCOS ends, and more preferably, on a flat portion, and does not overlap the LOCOS ends. The reasons for this are that the LOCOS ends tend to have a crystalline defect due to a stress generated in the LOCOS forming stage so that a leak current attributed to the crystalline defect occurs; that extension of the bird's beak is difficult to control due to the attributes of the process; and that a stable channel implantation is difficult when the channel includes a raised portion of the LOCOS end.
Third, in order to form the source/drain regions by self aligned implantation, it is required that side surfaces of the gate electrode are perpendicular to the substrate surface.
Fourth, the technique using two masks for the formation of the recess and the formation of the gate electrode requires a margin accordingly. Therefore, such a technique is not appropriate for the promotion of fineness. This technique also may cause a variation of characteristics due to a deviation of the gate electrode. Therefore, to promote the fineness and stabilize the characteristics, the recess and the gate electrode are required to be formed by a self-alignment technique.
Fifth, when employing the salicide technique, in order to prevent a short-circuit due to the bridging of the source/drain regions and the gate by the silicide, it is required that the gate electrode is provided with side walls of a CVD insulation film. Therefore, the side surfaces of the gate electrode are required to have a certain perpendicularity to the substrate surface and a certain height, similarly to the case of the self aligned implantation into the source/drain regions.
Studying the above-mentioned prior arts taking the above in consideration, the prior art shown in FIGS. 5A through 5D is not of the self-alignment type although it uses the LOCOS technique, meaning that it does not meet the aforementioned fourth requirement. Furthermore, a channel region exists at the LOCOS ends, so that the second requirement is not met. Therefore, this prior art has the problem of a leak current and deterioration of the characteristics of the field-effect transistor.
Regarding the prior art shown in FIGS. 6A through 6D, the recessed structure is formed not by the LOCOS technique but by directly etching the SOI layer by the dry etching technique, meaning that the first requirement is not met. Furthermore, the surface of the gate electrode and the surface of the source/drain regions are located at approximately identical levels, i.e., the gate electrode is buried in the recess. Therefore, if the salicide technique is employed, there is a strong possibility that bridging occurs, resulting in that the gate and the source and drain regions are short-circuited.
With respect to the prior art shown in FIGS. 7A through 7D, the above second, third and fifth requirements are not met. That is, the gate electrode overlaps the LOCOS ends and the gate electrode side surfaces are not perpendicular. Therefore, the implantation into the source and drain regions and the implantation into the channel region are difficult to control. Furthermore, when the salicide technique is employed, it is difficult to form the side walls on the gate electrode side surfaces since the gate electrode side surfaces are not perpendicular to the substrate surface.